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Searched refs:MHPMEVENTH_BIT_VSINH (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h925 #define MHPMEVENTH_BIT_VSINH BIT(27) macro
938 MHPMEVENTH_BIT_VSINH | \
H A Dpmu.c115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv32()
H A Dcsr.c997 riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; in write_mhpmeventh()