Searched refs:MG_REFCLKIN_CTL_OD_2_MUX_MASK (Results 1 – 2 of 2) sorted by relevance
162 #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) macro
3419 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()3487 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()3664 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); in icl_mg_pll_write()3707 val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_write()