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Searched refs:MFFS (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/tests/tcg/ppc64/
H A Dmffsce.c6 #define MFFS(FRT) asm("mffs %0" : "=f" (FRT)) macro
25 MFFS(fpscr); /* read the value that mffsce stored to cpu fpscr */ in main()
H A Dmtfsf.c8 #define MFFS(FRT) asm("mffs %0" : "=f" (FRT)) macro
45 MFFS(fpscr); in main()
/openbmc/linux/arch/powerpc/math-emu/
H A Dmath.c147 #define MFFS 0x247 /* 583 */ macro
319 case MFFS: func = mffs; type = X; break; in do_mathemu()
/openbmc/qemu/target/ppc/translate/
H A Dfp-impl.c.inc515 * Before Power ISA v3.0, MFFS bits 11~15 were reserved, any instruction
516 * with OPCD=63 and XO=583 should be decoded as MFFS.
/openbmc/qemu/target/ppc/
H A Dinsn32.decode558 # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored
561 MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc