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Searched refs:MCTL_DIV2 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c529 #define MCTL_DIV2(n) ((n + 1)/2) in mctl_channel_init() macro
533 writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) | in mctl_channel_init()
536 writel((MCTL_DIV2(tXP) << 16) | (MCTL_DIV2(tRTP) << 8) | in mctl_channel_init()
537 (MCTL_DIV2(tRC) << 0), in mctl_channel_init()
539 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
540 (MCTL_DIV2(RD2WR) << 8) | (MCTL_DIV2(WR2RD) << 0), in mctl_channel_init()
546 writel((MCTL_DIV2(tMRD) << 12) | (MCTL_DIV2(tMOD) << 0), in mctl_channel_init()
548 writel((MCTL_DIV2(tRCD) << 24) | (MCTL_DIV2(tCCD) << 16) | in mctl_channel_init()
549 (MCTL_DIV2(tRRD) << 8) | (MCTL_DIV2(tRP) << 0), in mctl_channel_init()
551 writel((MCTL_DIV2(tCKSRX) << 24) | (MCTL_DIV2(tCKSRE) << 16) | in mctl_channel_init()
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