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Searched refs:MCTL (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/adc/
H A Dzynq-xadc.c31 MCTL, enumerator
102 s->regs[MCTL] = MCTL_RESET; in zynq_xadc_reset()
142 case MCTL: in zynq_xadc_check_offset()
170 case MCTL: in zynq_xadc_read()
219 if (s->regs[MCTL] & MCTL_RESET) { in zynq_xadc_write()
244 case MCTL: in zynq_xadc_write()
245 s->regs[MCTL] = val & 0x00fffeff; in zynq_xadc_write()
/openbmc/linux/drivers/staging/most/dim2/
H A Dreg.h48 u32 MCTL; /* 0x38 */ member
H A Dhal.c150 while ((readl(&g.dim2->MCTL) & 1) != 1) in dim2_transfer_madr()
153 writel(0, &g.dim2->MCTL); /* clear transfer complete */ in dim2_transfer_madr()
163 writel(0, &g.dim2->MCTL); /* clear transfer complete */ in dim2_clear_dbr()
181 writel(0, &g.dim2->MCTL); /* clear transfer complete */ in dim2_write_ctr_mask()