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Searched refs:MCFSIM_ICR_LEVEL5 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/arch/m68k/include/asm/
H A Dmcfintc.h37 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ macro
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5307.h59 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ macro
H A Dm5249.h131 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ macro
/openbmc/linux/arch/m68k/coldfire/
H A Dm5407.c43 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m5407_i2c_init()
H A Dm5206.c43 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m5206_i2c_init()
H A Dm5307.c52 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m5307_i2c_init()
H A Dm525x.c64 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m525x_i2c_init()
H A Dm5249.c92 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m5249_i2c_init()