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Searched refs:MCFSIM_ICR0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h47 #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ macro
113 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
/openbmc/linux/arch/m68k/include/asm/
H A Dm5407sim.h38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ macro
113 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
H A Dm5307sim.h38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ macro
149 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
H A Dm525xsim.h42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ macro
144 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
H A Dm53xxsim.h51 #define MCFSIM_ICR0 0xFC048040 macro
67 #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */