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Searched refs:MAX_PHASE_RL_UL_1TO1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.h182 #define MAX_PHASE_RL_UL_1TO1 0 macro
H A Dddr3_read_leveling.c559 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_rl_mode()
983 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_window_mode()