Searched refs:MAX_CS_NUM (Results 1 – 10 of 10) sorted by relevance
72 enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM];73 enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM];83 enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM];84 enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM];
18 static u32 ui_xor_regs_base_backup[MAX_CS_NUM + 1];19 static u32 ui_xor_regs_mask_backup[MAX_CS_NUM + 1];27 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()30 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_init()99 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_finish()102 for (ui = 0; ui < MAX_CS_NUM + 1; ui++) in mv_sys_xor_finish()
212 for (cs = 0; cs < MAX_CS_NUM; cs++) { in mv_ddr_cs_num_get()305 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_park_get()322 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_rtt_wr_get()
47 u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) in ddr3_tip_dynamic_read_leveling()816 u8 wl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_write_leveling()1675 enum rl_dqs_burst_state rl_state[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1687 u32 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1688 u32 rl_min_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1689 u32 rl_max_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM] = { { {0} } }; in mv_ddr_rl_dqs_burst()1690 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst()
9 #define MAX_CS_NUM 4 macro
91 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];92 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];93 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];809 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
1037 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_fast_path_dynamic_cs_size_config()1126 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_restore_and_set_final_windows()1173 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_save_and_set_training_windows()
16 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];23 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
494 for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) { in hws_ddr3_tip_init_controller()1932 for (cs = 0; cs < MAX_CS_NUM; cs++) { in ddr3_tip_ddr3_reset_phy_regs()2874 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_p_get()2889 if (cs_num > 0 && cs_num <= MAX_CS_NUM) in mv_ddr_misl_phy_odt_n_get()
47 u32 read_sample[MAX_CS_NUM]; in ddr3_tip_write_additional_odt_setting()