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Searched refs:MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7672 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 macro
H A Ddce_8_0_sh_mask.h8152 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 macro
H A Ddce_10_0_sh_mask.h7216 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 macro
H A Ddce_11_0_sh_mask.h7106 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 macro
H A Ddce_11_2_sh_mask.h8218 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 macro
H A Ddce_12_0_sh_mask.h5113 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1744 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h2839 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2638 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_1_0_sh_mask.h4132 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h2323 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h1680 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h2890 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2799 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10953 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2896 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2906 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT … macro