Searched refs:MAILBOX_CONTROL (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_vi.c | 323 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack()
326 reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); in xgpu_vi_mailbox_send_ack()
348 reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, in xgpu_vi_mailbox_set_valid()
370 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg()
392 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | aquantia.c | 44 #define MAILBOX_CONTROL 0x0200 macro
138 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC); in aquantia_load_memory()
152 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, in aquantia_load_memory()
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