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Searched refs:M7 (Results 1 – 25 of 79) sorted by relevance

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/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h33 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
34 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
35 { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
37 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
51 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
52 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
53 { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
54 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
55 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
56 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
[all …]
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.h28 MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
29 MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
30 MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
31 MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
32 MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
33 MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
34 MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
35 MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
38 MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
41 MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
[all …]
/openbmc/u-boot/board/lg/sniper/
H A Dsniper.h78 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
86 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M7)) /* safe_mode */ \
87 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \
88 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \
89 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \
98 MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)) /* safe_mode */ \
99 MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
100 MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)) /* safe_mode */ \
101 MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)) /* safe_mode */ \
108 MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)) /* safe_mode */ \
[all …]
/openbmc/u-boot/board/ti/am3517crane/
H A Dam3517crane.h82 MUX_VAL(CP(GPMC_A1), (M7))\
87 MUX_VAL(CP(GPMC_A6), (M7))\
90 MUX_VAL(CP(GPMC_A9), (M7))\
91 MUX_VAL(CP(GPMC_A10), (M7))\
110 MUX_VAL(CP(GPMC_NCS2), (M7))\
111 MUX_VAL(CP(GPMC_NCS3), (M7))\
112 MUX_VAL(CP(GPMC_NCS4), (M7))\
113 MUX_VAL(CP(GPMC_NCS5), (M7))\
114 MUX_VAL(CP(GPMC_NCS6), (M7))\
115 MUX_VAL(CP(GPMC_NCS7), (M7))\
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm7.inc2 # Tune Settings for Cortex-M7
6 TUNEVALID[cortexm7] = "Enable Cortex-M7 specific processor optimizations"
/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32h743-overview.rst8 The STM32H743 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @400MHz
H A Dstm32h750-overview.rst8 The STM32H750 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @480MHz
H A Dstm32f746-overview.rst8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
H A Dstm32f769-overview.rst8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
/openbmc/linux/Documentation/devicetree/bindings/rng/
H A Dsparc_sun_oracle_rng.txt12 - 'ORCL,m7-rng' for SPARC T7/M7
23 /* solaris on SPARC M7-8 */
/openbmc/phosphor-webui/app/assets/icons/
H A Dicon-check.svg1 <svg viewBox="0 0 17.75 17.75"><path d="M7 14.5L2 9.54l1.59-1.57L7 11.35 14.41 4 16 5.58 7 14.5z"/>…
H A Dicon-arrow--down.svg1 <svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 15 30"><g><path d="M7.5 30l7.5-7.5-1.76-1.76-4…
H A Dicon-arrow--up.svg1 <svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 15 30"><g><path d="M7.5 0L0 7.5l1.76 1.76 4.49…
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dmux_omap5.h46 #define M7 7 macro
48 #define SAFE_MODE M7
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dmux_omap4.h54 #define M7 7 macro
56 #define SAFE_MODE M7
/openbmc/linux/arch/arm64/crypto/
H A Dpolyval-ce-core.S45 M7 .req v7 label
224 ld1 {M4.16b, M5.16b, M6.16b, M7.16b}, [MSG], #64
226 karatsuba1 M7 KEY1
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-verdin-nonwifi.dtsi50 * Often used by the M7 and then should not be enabled here.
/openbmc/u-boot/board/freescale/lx2160a/
H A DREADME140 |Mezzanine:X-M7-40G (29738)
144 20 |Mezzanine:X-M7-40G (29738)
147 |Mezzanine:X-M7-40G (29738)
/openbmc/u-boot/board/logicpd/zoom1/
H A Dzoom1.h104 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
108 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero_mux_data.h186 {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
187 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h386 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
387 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
388 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
389 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
390 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
391 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
/openbmc/u-boot/arch/x86/include/asm/arch-braswell/
H A Dgpio.h21 M7, enumerator
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-qcom-dc-scm-v1.dts107 /*M0-M7*/ "","","","","","","","",
/openbmc/linux/Documentation/arch/sparc/oradax/
H A Doracle-dax.rst5 DAX is a coprocessor which resides on the SPARC M7 (DAX1) and M8
45 the M7 and later processors provide a mechanism to pause the virtual
101 On a DAX1 system (M7), the device will be called "oradax1", while on a
167 new M7/M8 processor capabilities to efficiently poll this status byte.
273 First, the proper device must be opened. For M7 it will be
/openbmc/linux/drivers/sbus/char/
H A DKconfig74 It is available on M7 and M8 based systems only.

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