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Searched refs:LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7660 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 macro
H A Ddce_8_0_sh_mask.h3212 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 macro
H A Ddce_10_0_sh_mask.h3134 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 macro
H A Ddce_11_0_sh_mask.h3204 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 macro
H A Ddce_11_2_sh_mask.h3452 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 macro
H A Ddce_12_0_sh_mask.h9275 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21272 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43260 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40026 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42542 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49138 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48769 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT … macro