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Searched refs:LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7655 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L macro
H A Ddce_8_0_sh_mask.h3203 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 macro
H A Ddce_10_0_sh_mask.h3125 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 macro
H A Ddce_11_0_sh_mask.h3195 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 macro
H A Ddce_11_2_sh_mask.h3443 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 macro
H A Ddce_12_0_sh_mask.h9277 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21274 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43262 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
H A Ddcn_1_0_sh_mask.h40028 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42544 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48771 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49140 #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK … macro