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Searched refs:LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7650 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 macro
H A Ddce_8_0_sh_mask.h3216 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 macro
H A Ddce_10_0_sh_mask.h3138 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 macro
H A Ddce_11_0_sh_mask.h3208 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 macro
H A Ddce_11_2_sh_mask.h3456 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 macro
H A Ddce_12_0_sh_mask.h9284 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21281 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43269 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40035 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42551 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49147 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48778 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT … macro