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Searched refs:LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7649 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L macro
H A Ddce_8_0_sh_mask.h3215 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_10_0_sh_mask.h3137 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_11_0_sh_mask.h3207 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_11_2_sh_mask.h3455 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 macro
H A Ddce_12_0_sh_mask.h9286 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21283 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43271 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
H A Ddcn_1_0_sh_mask.h40037 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42553 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48780 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49149 #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK … macro