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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7632 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 macro
H A Ddce_8_0_sh_mask.h3184 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 macro
H A Ddce_10_0_sh_mask.h3106 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 macro
H A Ddce_11_0_sh_mask.h3176 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 macro
H A Ddce_11_2_sh_mask.h3424 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 macro
H A Ddce_12_0_sh_mask.h9248 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21245 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43233 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
H A Ddcn_1_0_sh_mask.h39999 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42515 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48742 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49111 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT … macro