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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7631 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a macro
H A Ddce_8_0_sh_mask.h3188 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa macro
H A Ddce_10_0_sh_mask.h3110 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa macro
H A Ddce_11_0_sh_mask.h3180 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa macro
H A Ddce_11_2_sh_mask.h3428 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa macro
H A Ddce_12_0_sh_mask.h9250 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21247 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43235 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40001 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42517 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49113 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48744 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT … macro