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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7627 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L macro
H A Ddce_8_0_sh_mask.h3183 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 macro
H A Ddce_10_0_sh_mask.h3105 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 macro
H A Ddce_11_0_sh_mask.h3175 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 macro
H A Ddce_11_2_sh_mask.h3423 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 macro
H A Ddce_12_0_sh_mask.h9260 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21257 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43245 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
H A Ddcn_1_0_sh_mask.h40011 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42527 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48754 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49123 #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK … macro