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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7614 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 macro
H A Ddce_8_0_sh_mask.h3196 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 macro
H A Ddce_10_0_sh_mask.h3118 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 macro
H A Ddce_11_0_sh_mask.h3188 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 macro
H A Ddce_11_2_sh_mask.h3436 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 macro
H A Ddce_12_0_sh_mask.h9254 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h21251 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43239 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
H A Ddcn_1_0_sh_mask.h40005 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h42521 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49117 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48748 #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT … macro