| /openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/ |
| H A D | python3-lrparsing_1.0.17.bb | 1 SUMMARY = "Python LR parsing library"
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/byacc/ |
| H A D | byacc.inc | 3 …"A parser generator utility that reads a grammar specification from a file and generates an LR(1) \
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| /openbmc/qemu/target/hexagon/idef-parser/ |
| H A D | idef-parser.lex | 341 "LR" { yylval->rvalue.type = REGISTER;
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| H A D | macros.h.inc | 97 #define fWRITE_LR(A) (LR = A)
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_rva.c.inc | 47 * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
98 * an SC to any address, in between an LR and SC pair.
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | omap3-evm-common.dtsi | 105 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | vectors.S | 209 stmdb r8, {sp, lr}^ @ Calling SP, LR
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| /openbmc/docs/designs/ |
| H A D | cable-monitor.md | 40 flowchart LR
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| H A D | liquid-leak-detection.md | 79 flowchart LR
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| /openbmc/openbmc/poky/meta/recipes-support/libunwind/libunwind/ |
| H A D | 0004-Rework-inline-aarch64-as-for-setcontext.patch | 141 - [x30] "m"(uc->uc_mcontext.regs[30]), /* LR */
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| /openbmc/qemu/target/hexagon/ |
| H A D | attribs_def.h.inc | 103 DEF_ATTRIB(IMPLICIT_WRITES_LR, "Writes the link register", "", "UREG.LR")
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| /openbmc/openbmc/meta-raspberrypi/recipes-graphics/userland/files/ |
| H A D | 0003-wayland-Add-Wayland-example.patch | 74 …QZ&9@5EL:JQ?OVBRYEU\<LS@PWCTZ3<FEOY1;EDNW07@18A39?27>1:C=FOHU]BSZFV\CSYESY@LR>GOBKS3?ELW_ERZ>ITM]f…
75 …*���u��ASeAUY?PXBU[@PZDV]=PU@SVCVX=QVAUZ?OU=KQ>MS@LR=JPBJR=LN8HJ8CG4AD0;>+7:6?B=FJ6<ABGL/9<ENR=HL3…
76 …LR<HMBQT>MT9KS=OV<OTASU>OS|��k��D]m3L\4M]7OaBZlOgyn��x��s��\u�Ict-H\,Gb4S4GX,CS��ċ��z�����}������…
77 …�u��v����������ˍ�ą�������w��l��<Xi4N]4M^1GV/EP.EQ9IV7HU<LW8GT5FO>NU9IN=MS<LR<LR9JP@NT=KQ>MS>JP:FL…
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 651 #define LR SPRN_LR macro
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | t32.decode | 410 # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
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| /openbmc/libpldm/docs/checklists/ |
| H A D | changes.md | 129 direction LR
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| /openbmc/qemu/tcg/ppc/ |
| H A D | tcg-target.c.inc | 497 #define LR SPR(8, 0)
2175 tcg_out32(s, MFSPR | RT(arg) | LR);
2599 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
2626 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
2641 tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR);
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| /openbmc/libpldm/ |
| H A D | CONTRIBUTING.md | 129 direction LR
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/ |
| H A D | 0001-BootLogoLib-align-logo-coords-to-be-even.patch | 250 zYe74*qpliP`@TQkQ?&7j`kGx!LR(WKrC&*GBO=wcEL*!k9W5sE4c{WIr}mAg6uPQG
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/fbida/files/ |
| H A D | support-jpeg-turbo.patch | 1693 - JXFORM_TRANSPOSE, /* transpose across UL-to-LR axis */
1755 + JXFORM_TRANSPOSE, /* transpose across UL-to-LR axis */
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| /openbmc/qemu/hw/intc/ |
| H A D | trace-events | 171 … idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d …
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| /openbmc/qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 3449 /* Push (FP, LR) and allocate space for all saved registers. */
3506 /* Pop (FP, LR), restore SP to previous frame. */
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| /openbmc/qemu/tcg/arm/ |
| H A D | tcg-target.c.inc | 1605 * opcode into LR for the slow path. We will not be using
1639 * opcode into LR for the slow path. We will not be using
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| /openbmc/qemu/target/s390x/tcg/ |
| H A D | insn-data.h.inc | 417 C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0)
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| /openbmc/qemu/tcg/s390x/ |
| H A D | tcg-target.c.inc | 886 tcg_out_insn(s, RR, LR, dst, src);
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| /openbmc/libcper/specification/document/ |
| H A D | cper-json-specification.tex | 976 r14\_lr & uint64 & Register R14 (LR). \texttt{UINT32} value null extended to \texttt{UINT64}.\\
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