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Searched refs:LPDDR4_TRAIN_SEQ_100 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dlpddr4_define.h41 #define LPDDR4_TRAIN_SEQ_100 0x121f macro
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c526 { 0x54008, LPDDR4_TRAIN_SEQ_100 },