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Searched refs:LPDDR4_RTT_CA_BANK1 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c358 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
383 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
435 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
460 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
513 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
538 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
H A Dlpddr4_timing.c374 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
415 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
638 (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
672 { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dlpddr4_define.h86 #define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 macro