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Searched refs:LPDDR4_RTT_CA_BANK0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c351 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
377 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
429 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
454 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
506 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
532 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
H A Dlpddr4_timing.c363 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
400 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
627 (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
662 { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dlpddr4_define.h85 #define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 macro