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Searched refs:LPDDR4_HDT_CTL_100_1D (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dlpddr4_define.h35 #define LPDDR4_HDT_CTL_100_1D 0xC8 macro
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c527 { 0x54009, LPDDR4_HDT_CTL_100_1D },