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Searched refs:LPDDR3 (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3288.c249 case LPDDR3: in pctl_cfg()
318 case LPDDR3: in phy_cfg()
486 if (sdram_params->base.dramtype != LPDDR3) in data_training()
526 if (sdram_params->base.dramtype != LPDDR3) in data_training()
657 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
790 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
832 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
871 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
892 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
H A Dsdram_rk3399.c176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
311 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
400 else if (sdram_params->base.dramtype == LPDDR3) in phy_io_config()
869 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
1047 (dramtype == LPDDR3 && ddr_freq > 933) || in sdram_init()
1068 if (dramtype == LPDDR3) in sdram_init()
H A Dsdram_rk3188.c428 if (sdram_params->base.dramtype != LPDDR3) in data_training()
468 if (sdram_params->base.dramtype != LPDDR3) in data_training()
604 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
776 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
H A Dsdram_rk322x.c222 if (dramtype == LPDDR3) in memory_init()
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
/openbmc/u-boot/drivers/ram/stm32mp1/
H A DKconfig10 family: support for LPDDR2, LPDDR3 and DDR3
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3399.h12 LPDDR3 = 0x6, enumerator
H A Dsdram.h13 LPDDR3 = 6, enumerator
H A Dsdram_rk322x.h13 LPDDR3 = 6, enumerator
/openbmc/u-boot/board/google/
H A DKconfig48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A DKconfig45 * 2GiB/4GiB LPDDR3 RAM
/openbmc/u-boot/board/vamrs/rock960_rk3399/
H A DREADME37 * DRAM: 2GB/4GB LPDDR3 @ 1866MHz
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt108 DRAM type (3=DDR3, 6=LPDDR3)
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c445 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) in sunxi_dram_init()
H A DKconfig380 bool "LPDDR3 with Allwinner stock configuration"
383 This option is the LPDDR3 timing used by the stock boot0 by
402 Set the dram type, 3: DDR3, 7: LPDDR3
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c34 DRAM_TYPE_STR(LPDDR3), in intel_dram_type_str()
/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME7 * 1GB 800MHz LPDDR3 DRAM
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-sdram-lpddr3-samsung-4GB-1866.dtsi43 6 /* LPDDR3 */