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Searched refs:LOG_GUEST_ERROR (Results 1 – 25 of 400) sorted by relevance

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/openbmc/qemu/target/microblaze/
H A Dmmu.c67 qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid); in mmu_change_pid()
123 qemu_log_mask(LOG_GUEST_ERROR, in mmu_translate()
189 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); in mmu_read()
193 qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n"); in mmu_read()
202 qemu_log_mask(LOG_GUEST_ERROR, in mmu_read()
215 qemu_log_mask(LOG_GUEST_ERROR, in mmu_read()
225 qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); in mmu_read()
228 qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn); in mmu_read()
246 qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); in mmu_write()
250 qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n"); in mmu_write()
[all …]
/openbmc/qemu/hw/misc/
H A Daspeed_sbc.c70 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_read()
90 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_otp_read()
100 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_otp_read()
113 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_otp_read()
134 qemu_log_mask(LOG_GUEST_ERROR, in mode_handler()
166 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_otp_prog()
185 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_handle_command()
205 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_handle_command()
223 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_write()
232 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sbc_write()
H A Dsbsa_ec.c34 qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: no readable registers"); in sbsa_ec_read()
50 qemu_log_mask(LOG_GUEST_ERROR, in sbsa_ec_write()
54 qemu_log_mask(LOG_GUEST_ERROR, "sbsa-ec: unknown EC register"); in sbsa_ec_write()
H A Darmsse-mhu.c86 qemu_log_mask(LOG_GUEST_ERROR, in armsse_mhu_read()
93 qemu_log_mask(LOG_GUEST_ERROR, in armsse_mhu_read()
126 qemu_log_mask(LOG_GUEST_ERROR, in armsse_mhu_write()
132 qemu_log_mask(LOG_GUEST_ERROR, in armsse_mhu_write()
H A Daspeed_sli.c27 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sli_read()
44 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sli_write()
60 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sliio_read()
77 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_sliio_write()
/openbmc/qemu/hw/timer/
H A Dsh_timer.c79 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", in sh_timer_read()
136 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
150 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
163 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
173 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
180 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
199 qemu_log_mask(LOG_GUEST_ERROR, in sh_timer_write()
270 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_read()
290 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_read()
303 qemu_log_mask(LOG_GUEST_ERROR, in tmu012_write()
[all …]
/openbmc/qemu/hw/virtio/
H A Dvirtio-mmio.c143 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
180 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
190 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
203 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
233 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
238 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_read()
298 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
314 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
334 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
364 qemu_log_mask(LOG_GUEST_ERROR, in virtio_mmio_write()
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_i2c.c32 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid bus number %d/%d\n", port, in pnv_i2c_get_bus()
52 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_update_irq()
134 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_flush()
175 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid command 0x%"PRIx64"\n", in pnv_i2c_handle_cmd()
182 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n"); in pnv_i2c_handle_cmd()
187 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_handle_cmd()
226 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_in()
232 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n"); in pnv_i2c_fifo_in()
238 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read command in progress\n"); in pnv_i2c_fifo_in()
261 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); in pnv_i2c_fifo_out()
[all …]
H A Dpnv_chiptod.c163 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: received TTYPE4 in " in chiptod_receive_ttype()
242 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power9_tx_ttype_target()
267 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressing: " in chiptod_power10_tx_ttype_target()
318 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
328 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
337 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: LOAD_TOG_REG in " in pnv_chiptod_xscom_write()
356 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
360 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
364 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
382 qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" in pnv_chiptod_xscom_write()
[all …]
/openbmc/qemu/hw/net/
H A Dnpcm_pcs.c154 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_read_sr_ctl()
169 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_read_sr_mii()
184 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_read_sr_tim()
199 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_read_vr_mii()
214 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_write_sr_ctl()
229 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_write_sr_mii()
249 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_write_sr_tim()
264 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_write_vr_mii()
300 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_read()
340 qemu_log_mask(LOG_GUEST_ERROR, in npcm_pcs_write()
H A Dftgmac100.c368 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", in do_phy_read()
413 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", in do_phy_write()
445 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", in do_phy_new_ctl()
463 qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n", in do_phy_ctl()
472 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%" in ftgmac100_read_bd()
493 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%" in ftgmac100_write_bd()
507 qemu_log_mask(LOG_GUEST_ERROR, in ftgmac100_insert_vlan()
515 qemu_log_mask(LOG_GUEST_ERROR, in ftgmac100_insert_vlan()
565 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid segment size\n", in ftgmac100_do_tx()
570 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n", in ftgmac100_do_tx()
[all …]
/openbmc/qemu/target/arm/
H A Darm-powerctl.c46 qemu_log_mask(LOG_GUEST_ERROR, in arm_get_cpu_by_id()
129 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on()
167 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on()
220 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on_and_reset()
233 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_on_and_reset()
273 qemu_log_mask(LOG_GUEST_ERROR, in arm_set_cpu_off()
310 qemu_log_mask(LOG_GUEST_ERROR, in arm_reset_cpu()
/openbmc/qemu/hw/char/
H A Davr_usart.c76 LOG_GUEST_ERROR, in update_char_mask()
83 LOG_GUEST_ERROR, in update_char_mask()
146 LOG_GUEST_ERROR, in avr_usart_read()
196 LOG_GUEST_ERROR, in avr_usart_write()
225 LOG_GUEST_ERROR, in avr_usart_write()
230 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad USART mode\n", __func__); in avr_usart_write()
234 LOG_GUEST_ERROR, in avr_usart_write()
248 LOG_GUEST_ERROR, in avr_usart_write()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_its.c367 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
377 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
385 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
396 qemu_log_mask(LOG_GUEST_ERROR, in lookup_ite()
417 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid ICID 0x%x\n", who, icid); in lookup_cte()
424 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid CTE\n", who); in lookup_cte()
446 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid VPEID 0x%x\n", who, vpeid); in lookup_vte()
454 qemu_log_mask(LOG_GUEST_ERROR, in lookup_vte()
492 qemu_log_mask(LOG_GUEST_ERROR, "%s: intid 0x%x out of range\n", in process_its_cmd_virt()
536 qemu_log_mask(LOG_GUEST_ERROR, in do_process_its_cmd()
[all …]
H A Dxive2.c110 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n", in xive2_presenter_nvgc_backlog_op()
115 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx); in xive2_presenter_nvgc_backlog_op()
155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx); in xive2_presenter_nvp_backlog_op()
159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx); in xive2_presenter_nvp_backlog_op()
232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" in xive2_end_queue_pic_print_info()
374 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" in xive2_end_enqueue()
444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", in xive2_presenter_backlog_scan()
449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", in xive2_presenter_backlog_scan()
481 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", in xive2_presenter_backlog_decr()
486 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", in xive2_presenter_backlog_decr()
[all …]
H A Darm_gicv2m.c76 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_read: bad size %u\n", size); in gicv2m_read()
97 qemu_log_mask(LOG_GUEST_ERROR, in gicv2m_read()
109 qemu_log_mask(LOG_GUEST_ERROR, "gicv2m_write: bad size %u\n", size); in gicv2m_write()
124 qemu_log_mask(LOG_GUEST_ERROR, in gicv2m_write()
H A Daspeed_vic.c66 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", in aspeed_vic_set_irq()
166 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_read()
172 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_read()
252 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
271 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
277 qemu_log_mask(LOG_GUEST_ERROR, in aspeed_vic_write()
/openbmc/qemu/hw/misc/macio/
H A Dpmu.c110 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_int_ack()
119 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_int_ack()
142 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_set_int_mask()
176 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_adb()
194 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_adb()
212 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_adb()
217 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n"); in pmu_cmd_adb()
250 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_adb_poll_off()
266 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_shutdown()
278 qemu_log_mask(LOG_GUEST_ERROR, in pmu_cmd_shutdown()
[all …]
/openbmc/qemu/hw/vmapple/
H A Daes.c229 qemu_log_mask(LOG_GUEST_ERROR, "%s: No payload\n", __func__); in cmd_key()
288 qemu_log_mask(LOG_GUEST_ERROR, "%s: No payload\n", __func__); in cmd_data()
294 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid key or iv\n", __func__); in cmd_data()
305 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA read of %"PRIu32" bytes " in cmd_data()
324 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid key length\n", __func__); in cmd_data()
331 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to create cipher object\n", in cmd_data()
338 qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to set IV\n", __func__); in cmd_data()
344 qemu_log_mask(LOG_GUEST_ERROR, "%s: Encryption failed\n", __func__); in cmd_data()
349 qemu_log_mask(LOG_GUEST_ERROR, "%s: Decryption failed\n", __func__); in cmd_data()
357 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA write of %"PRIu32" bytes " in cmd_data()
[all …]
/openbmc/qemu/hw/ssi/
H A Dsifive_spi.c186 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read at address 0x%" in sifive_spi_read()
224 qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write at addr=0x%" in sifive_spi_write()
233 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csid %d\n", in sifive_spi_write()
243 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csdef %x\n", in sifive_spi_write()
252 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid csmode %x\n", in sifive_spi_write()
269 qemu_log_mask(LOG_GUEST_ERROR, in sifive_spi_write()
277 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid watermark %d\n", in sifive_spi_write()
H A Dpnv_spi.c33 qemu_log_mask(LOG_GUEST_ERROR, \
71 qemu_log_mask(LOG_GUEST_ERROR, "Invalid offset = %d used to get byte " in get_from_offset()
94 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: Reading empty RX_FIFO\n"); in read_from_frame()
121 qemu_log_mask(LOG_GUEST_ERROR, "Invalid response payload size in " in spi_response()
161 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: Reading empty" in spi_response()
208 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO underflow\n"); in transfer()
220 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: RX_FIFO is full\n"); in transfer()
306 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported N1 shift size when " in calculate_N1()
313 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported N1 shift size, " in calculate_N1()
381 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi: TX_FIFO is full\n"); in operation_shiftn1()
[all …]
/openbmc/qemu/hw/fsi/
H A Daspeed_apb2opb.c103 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_read()
159 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
176 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
183 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
190 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
219 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
226 qemu_log_mask(LOG_GUEST_ERROR, in fsi_aspeed_apb2opb_write()
240 qemu_log_mask(LOG_GUEST_ERROR, "%s: OPB %s failed @%08x\n", in fsi_aspeed_apb2opb_write()
/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_msi.c26 qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !"); in phb3_msi_ive_addr()
31 qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRIx64")", in phb3_msi_ive_addr()
56 qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64, in phb3_msi_read_ive()
77 qemu_log_mask(LOG_GUEST_ERROR, in phb3_msi_set_p()
94 qemu_log_mask(LOG_GUEST_ERROR, in phb3_msi_set_q()
166 qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src); in pnv_phb3_msi_send()
175 qemu_log_mask(LOG_GUEST_ERROR, in pnv_phb3_msi_send()
/openbmc/qemu/hw/display/
H A Dvirtio-gpu-virgl.c108 qemu_log_mask(LOG_GUEST_ERROR, "%s: hostmem disabled\n", __func__); in virtio_gpu_virgl_map_resource_blob()
114 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map virgl resource: %s\n", in virtio_gpu_virgl_map_resource_blob()
171 qemu_log_mask(LOG_GUEST_ERROR, in virtio_gpu_virgl_unmap_resource_blob()
204 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", in virgl_cmd_create_resource_2d()
212 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n", in virgl_cmd_create_resource_2d()
252 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", in virgl_cmd_create_resource_3d()
260 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n", in virgl_cmd_create_resource_3d()
302 qemu_log_mask(LOG_GUEST_ERROR, "%s: resource does not exist %d\n", in virgl_cmd_resource_unref()
342 qemu_log_mask(LOG_GUEST_ERROR, "%s: context_init disabled", in virgl_cmd_context_create()
410 qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d", in virgl_cmd_set_scanout()
[all …]
/openbmc/qemu/target/ppc/
H A Dtimebase_helper.c361 qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: MOVE_CHIP_TOD_TO_TB " in tb_state_machine_step()
410 qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: LOAD_TOD_MOD and " in helper_store_tfmr()
434 qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: mtspr TFMR in TB_ERROR" in helper_store_tfmr()
449 qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: MOVE_CHIP_TOD_TO_TB " in helper_store_tfmr()
472 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); in helper_load_dcr()
483 qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", in helper_load_dcr()
496 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); in helper_store_dcr()
506 qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", in helper_store_dcr()

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