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Searched refs:LE_SF (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_link_encoder.h166 LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
167 LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
168 LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
169 LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
179 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
180 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\
181 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\
182 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\
183 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dio_link_encoder.h44 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
45 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
46 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
47 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
62 LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
63 LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
64 LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
143 LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
168 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
180 LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_link_encoder.h38 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
40 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_RX_VREF_CTRL, mask_sh),\
43 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL15, RDPCS_PHY_SUP_PRE_HP, mask_sh),\
48 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
60 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
61 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
64 LE_SF(DCIO_SOFT_RESET, UNIPHYA_SOFT_RESET, mask_sh),\
65 LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
66 LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
67 LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.h34 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
35 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DPALT_DP4, mask_sh),\
36 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_PSTATE, mask_sh),\
37 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_PSTATE, mask_sh),\
38 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_MPLL_EN, mask_sh),\
39 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_MPLL_EN, mask_sh),\
40 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_WIDTH, mask_sh),\
41 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_RATE, mask_sh),\
42 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_WIDTH, mask_sh),\
43 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_RATE, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h173 #define LE_SF(reg_name, field_name, post_fix)\ macro
179 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
190 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
191 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
192 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
193 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
194 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
195 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
196 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
197 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.h60 LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
64 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_HDMI_FRL_MODE, mask_sh),\
65 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP_10_BIT, mask_sh),\
66 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
67 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
68 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.h62 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
63 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
64 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh),\
65 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
66 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_link_encoder.h37 LE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, mask_sh)