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Searched refs:LANE_PLL_ENABLE (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c339 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
345 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
351 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
357 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
H A Dpsb_intel_reg.h1327 #define LANE_PLL_ENABLE (0x3 << 20) macro