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Searched refs:KS2_PASSPLLCTL0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c29 [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
305 reg = KS2_PASSPLLCTL0; in pll_freq_get()
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h177 #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) macro