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Searched refs:KS2_DDRPHY_PLLCR_OFFSET (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h31 #define KS2_DDRPHY_PLLCR_OFFSET 0x18 macro
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()