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Searched refs:KS2_DDR3_PLLCTRL_PHY_RESET (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c364 tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; in ddr3_reset_ddrphy()
372 tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; in ddr3_reset_ddrphy()
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h93 #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 macro