/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | cru_rk3399.h | 70 #define KHz 1000 macro 88 #define PERIHP_ACLK_HZ (148500*KHz) 89 #define PERIHP_HCLK_HZ (148500*KHz) 90 #define PERIHP_PCLK_HZ (37125*KHz) 92 #define PERILP0_ACLK_HZ (99000*KHz) 93 #define PERILP0_HCLK_HZ (99000*KHz) 94 #define PERILP0_PCLK_HZ (49500*KHz) 96 #define PERILP1_HCLK_HZ (99000*KHz) 97 #define PERILP1_PCLK_HZ (49500*KHz)
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H A D | cru_rk3328.h | 48 #define KHz 1000 macro 58 #define PERIHP_ACLK_HZ (144000 * KHz) 59 #define PERIHP_HCLK_HZ (72000 * KHz) 60 #define PERIHP_PCLK_HZ (72000 * KHz)
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | ti,j721e-cpb-audio.yaml | 18 In order to support 48KHz and 44.1KHz family of sampling rates the parent 19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and 24 48KHz family: 28 44.1KHz family: 33 48KHz family: 85 - description: Parent for CPB_McASP auxclk (for 48KHz) 86 - description: Parent for CPB_McASP auxclk (for 44.1KHz) 88 - description: Parent for CPB_SCKI clock (for 48KHz) 89 - description: Parent for CPB_SCKI clock (for 44.1KHz) 111 - description: Parent for CPB_McASP auxclk (for 48KHz) [all …]
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H A D | ti,j721e-cpb-ivi-audio.yaml | 23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock 30 Clocking setup for 48KHz family: 37 Clocking setup for 44.1KHz family: 76 - description: Parent for CPB_McASP auxclk (for 48KHz) 77 - description: Parent for CPB_McASP auxclk (for 44.1KHz) 79 - description: Parent for CPB_SCKI clock (for 48KHz) 80 - description: Parent for CPB_SCKI clock (for 44.1KHz) 82 - description: Parent for IVI_McASP auxclk (for 48KHz) 83 - description: Parent for IVI_McASP auxclk (for 44.1KHz) 85 - description: Parent for IVI_SCKI clock (for 48KHz) [all …]
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H A D | wlf,wm8524.yaml | 7 title: Wolfson WM8524 24-bit 192KHz Stereo DAC
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-class-rtc-rtc0-device-rtc_calibration | 7 calibrate the AB8500.s 32KHz Real Time Clock. 12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
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/openbmc/linux/Documentation/translations/zh_CN/power/ |
H A D | energy-model.rst | 171 02 unsigned long *KHz) 176 07 freq = foo_get_freq_ceil(dev, *KHz); 187 18 *KHz = freq;
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/openbmc/linux/drivers/cpufreq/ |
H A D | cppc_cpufreq.c | 511 unsigned long *power, unsigned long *KHz) in cppc_get_cpu_power() argument 515 unsigned long prev_freq = *KHz; in cppc_get_cpu_power() 533 perf_prev = cppc_cpufreq_khz_to_perf(cpu_data, *KHz); in cppc_get_cpu_power() 553 *KHz = cppc_cpufreq_perf_to_khz(cpu_data, perf); in cppc_get_cpu_power() 554 perf_check = cppc_cpufreq_khz_to_perf(cpu_data, *KHz); in cppc_get_cpu_power() 562 while ((*KHz == prev_freq) || (step_check != step)) { in cppc_get_cpu_power() 564 *KHz = cppc_cpufreq_perf_to_khz(cpu_data, perf); in cppc_get_cpu_power() 565 perf_check = cppc_cpufreq_khz_to_perf(cpu_data, *KHz); in cppc_get_cpu_power() 579 static int cppc_get_cpu_cost(struct device *cpu_dev, unsigned long KHz, in cppc_get_cpu_cost() argument 594 perf_prev = cppc_cpufreq_khz_to_perf(cpu_data, KHz); in cppc_get_cpu_cost()
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H A D | scmi-cpufreq.c | 101 unsigned long *KHz) in scmi_get_cpu_power() argument 112 Hz = *KHz * 1000; in scmi_get_cpu_power() 122 *KHz = Hz / 1000; in scmi_get_cpu_power()
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H A D | mediatek-cpufreq-hw.c | 57 unsigned long *KHz) in mtk_cpufreq_get_cpu_power() argument 70 if (data->table[i].frequency < *KHz) in mtk_cpufreq_get_cpu_power() 75 *KHz = data->table[i].frequency; in mtk_cpufreq_get_cpu_power()
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/openbmc/linux/Documentation/devicetree/bindings/regulator/ |
H A D | richtek,rt6245-regulator.yaml | 63 Buck switch frequency selection. Each respective value means 400KHz, 64 800KHz, 1200KHz. If this property is missing then keep in chip default.
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/openbmc/linux/arch/arm/mach-omap1/ |
H A D | Kconfig | 67 bool "Use 32KHz timer" 71 Select this option if you want to enable the OMAP 32KHz timer. 73 support for no tick during idle. The 32KHz timer provides less 74 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 87 timer provides more intra-tick resolution than the 32KHz timer,
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/openbmc/qemu/target/xtensa/ |
H A D | import_core.sh | 10 Usage: $0 overlay-archive-to-import core-name [frequency-in-KHz] 15 frequency-in-KHz: core frequency (40MHz if not specified).
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | clk-palmas-clk32kg-clocks.txt | 1 * Palmas 32KHz clocks * 3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
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/openbmc/linux/drivers/media/dvb-frontends/ |
H A D | s5h1411.c | 376 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1411_set_if_freq() argument 380 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1411_set_if_freq() 382 switch (KHz) { in s5h1411_set_if_freq() 400 __func__, KHz); in s5h1411_set_if_freq() 410 state->if_freq = KHz; in s5h1411_set_if_freq()
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H A D | s5h1409.c | 353 static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz) in s5h1409_set_if_freq() argument 357 dprintk("%s(%d KHz)\n", __func__, KHz); in s5h1409_set_if_freq() 359 switch (KHz) { in s5h1409_set_if_freq() 373 state->if_freq = KHz; in s5h1409_set_if_freq()
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/openbmc/linux/arch/arm/boot/dts/allwinner/ |
H A D | sun5i-reference-design-tablet.dtsi | 88 * The gsl1680 is rated at 400KHz and it will not work reliable at 89 * 100KHz, this has been confirmed on multiple different q8 tablets. 90 * All other devices on this bus are also rated for 400KHz.
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | max77620.txt | 36 with internal regulators. 32KHz clock can be programmed to be part of a 46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power 54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz 58 and 32KHz clock get disabled at
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/openbmc/u-boot/arch/arm/dts/ |
H A D | sun5i-reference-design-tablet.dtsi | 89 * The gsl1680 is rated at 400KHz and it will not work reliable at 90 * 100KHz, this has been confirmed on multiple different q8 tablets. 91 * All other devices on this bus are also rated for 400KHz.
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/openbmc/u-boot/drivers/clk/rockchip/ |
H A D | clk_rk3399.c | 287 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 288 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 289 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 290 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() 366 u32 freq_khz = freq_hz / KHz; in pll_para_config() 412 if (best_diff_khz > 4 * (MHz/KHz)) { in pll_para_config() 415 best_diff_khz * KHz); in pll_para_config()
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H A D | clk_rk3328.c | 179 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 180 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 181 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 182 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
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/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | opencores,i2c-ocores.yaml | 45 frequency is fixed at 100 KHz. 109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
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/openbmc/u-boot/doc/device-tree-bindings/i2c/ |
H A D | i2c-gpio.txt | 18 It not defined, then default is 5us (~50KHz).
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/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | spreadtrum,sprd-timer.txt | 12 - clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock).
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/openbmc/linux/drivers/clk/pxa/ |
H A D | clk-pxa27x.c | 21 #define KHz 1000 macro 100 return (unsigned int)clks[0] / KHz; in pxa27x_get_clk_frequency_khz() 294 32768 * KHz)); in pxa27x_register_plls()
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