Searched refs:JZ4760_CLK_PLL1 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | jz4760-cgu.c | 116 [JZ4760_CLK_PLL1] = {
216 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
223 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
230 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
248 .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
259 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
267 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
274 JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | ingenic,jz4760-cgu.h | 13 #define JZ4760_CLK_PLL1 4 macro
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