Searched refs:JZ4740_CLK_PLL_HALF (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | jz4740-cgu.c | 94 [JZ4740_CLK_PLL_HALF] = {
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
183 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
190 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
197 .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | ingenic,jz4740-cgu.h | 18 #define JZ4740_CLK_PLL_HALF 3 macro
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