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Searched refs:JH7110_SYSCLK_VOUT_AXI (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c127 JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
128 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
130 JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h76 #define JH7110_SYSCLK_VOUT_AXI 59 macro