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Searched refs:JH7110_SYSCLK_UART1_CORE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h165 #define JH7110_SYSCLK_UART1_CORE 148 macro
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c250 JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi390 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,