Home
last modified time | relevance | path

Searched refs:JH7110_SYSCLK_UART0_CORE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h163 #define JH7110_SYSCLK_UART0_CORE 146 macro
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c248 JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi377 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,