Searched refs:JH7110_SYSCLK_DDR_BUS (Results 1 – 2 of 2) sorted by relevance
60 #define JH7110_SYSCLK_DDR_BUS 43 macro
99 JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,104 JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),