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Searched refs:JH7110_SYSCLK_AXI_CFG0_MAIN_DIV (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h100 #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 macro
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c157 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,