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Searched refs:JH7100_CLK_VENC_BUS (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7100.c118 JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
119 JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
120 JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive-jh7100.h65 #define JH7100_CLK_VENC_BUS 56 macro