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Searched refs:JH7100_CLK_UART3_CORE (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dstarfive-jh7100.h171 #define JH7100_CLK_UART3_CORE 162 macro
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi231 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7100.c244 JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),