| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_pps.c | 30 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_name()
348 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_num_pps()
397 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_initial_setup()
487 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
533 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
546 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1515 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1572 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1611 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in pps_init_late()
1668 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
[all …]
|
| H A D | g4x_dp.c | 72 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_set_clock()
470 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
655 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
665 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
1244 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1316 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_init()
1337 else if (IS_VALLEYVIEW(dev_priv)) in g4x_dp_init()
1346 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || in g4x_dp_init()
|
| H A D | intel_pipe_crc.c | 409 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
539 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
615 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
|
| H A D | intel_dsi_vbt.c | 495 else if (IS_VALLEYVIEW(dev_priv)) in mipi_exec_gpio()
969 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
975 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_init()
1030 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
1034 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_cleanup()
|
| H A D | intel_vga.c | 20 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
|
| H A D | intel_sprite_uapi.c | 63 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_sprite_set_colorkey_ioctl()
|
| H A D | intel_hotplug_irq.c | 139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
421 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
459 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
474 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
|
| H A D | intel_cdclk.c | 489 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
501 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
536 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
2600 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2609 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
3243 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3275 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3413 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3638 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
|
| H A D | i9xx_plane.c | 805 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
839 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
870 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
|
| H A D | intel_crt.c | 366 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_mode_valid()
582 if (IS_VALLEYVIEW(dev_priv)) in intel_crt_detect_hotplug()
1008 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_init()
|
| H A D | intel_crtc.c | 348 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) in intel_crtc_init()
539 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
|
| H A D | intel_lpe_audio.c | 187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
|
| H A D | g4x_hdmi.c | 664 if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) in is_hdmi_port_valid()
735 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_hdmi_init()
|
| H A D | intel_display.c | 174 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2059 else if (IS_VALLEYVIEW(dev_priv)) in i9xx_crtc_disable()
2704 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_set_pipeconf()
2738 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_set_pipeconf()
2915 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_get_pipe_config()
2933 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
2941 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_get_pipe_config()
2984 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in i9xx_get_pipe_config()
2998 else if (IS_VALLEYVIEW(dev_priv)) in i9xx_get_pipe_config()
4398 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in compute_baseline_pipe_bpp()
[all …]
|
| H A D | intel_drrs.c | 73 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_refresh_rate_pipeconf()
|
| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | vlv_sideband.c | 46 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
54 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
|
| H A D | vlv_suspend.c | 386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
431 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
461 if (!IS_VALLEYVIEW(i915)) in vlv_suspend_init()
|
| H A D | i915_irq.c | 1314 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
1339 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
1364 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
|
| /openbmc/linux/drivers/gpu/drm/i915/selftests/ |
| H A D | intel_uncore.c | 175 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
286 !IS_VALLEYVIEW(gt->i915) && in live_forcewake_domains()
|
| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_rc6.c | 619 else if (IS_VALLEYVIEW(i915)) in intel_rc6_init()
657 else if (IS_VALLEYVIEW(i915)) in intel_rc6_enable()
815 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
|
| H A D | selftest_rc6.c | 51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
|
| H A D | intel_rps.c | 705 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
842 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1546 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1646 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1663 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
1994 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
2081 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2110 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in __read_cagf()
|
| H A D | intel_gt_pm_debugfs.c | 324 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
355 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
|
| H A D | intel_ggtt_fencing.c | 579 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { in detect_bit_6_swizzle()
854 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) in intel_ggtt_init_fences()
|
| /openbmc/linux/drivers/gpu/drm/i915/soc/ |
| H A D | intel_gmch.c | 85 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()
|