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Searched refs:IRTL_VALID (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dcpu.c515 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; in configure_c_states()
520 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; in configure_c_states()
525 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; in configure_c_states()
530 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; in configure_c_states()
535 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; in configure_c_states()
540 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; in configure_c_states()
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dmodel_206ax.c255 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; in configure_c_states()
260 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; in configure_c_states()
265 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; in configure_c_states()
/openbmc/u-boot/arch/x86/include/asm/arch-ivybridge/
H A Dmodel_206ax.h35 #define IRTL_VALID (1 << 15) macro
/openbmc/u-boot/arch/x86/include/asm/
H A Dmsr-index.h171 #define IRTL_VALID (1 << 15) macro