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Searched refs:IREG_BASE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/net/wwan/t7xx/
H A Dt7xx_pcie_mac.c85 void __iomem *pbase = IREG_BASE(t7xx_dev); in t7xx_pcie_mac_atr_cfg()
142 t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), i); in t7xx_pcie_mac_atr_init()
152 t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), cfg.port); in t7xx_pcie_mac_atr_init()
166 t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), cfg.port); in t7xx_pcie_mac_atr_init()
182 value = ioread32(IREG_BASE(t7xx_dev) + ISTAT_HST_CTRL); in t7xx_pcie_mac_enable_disable_int()
189 iowrite32(value, IREG_BASE(t7xx_dev) + ISTAT_HST_CTRL); in t7xx_pcie_mac_enable_disable_int()
217 reg = IREG_BASE(t7xx_dev) + IMASK_HOST_MSIX_CLR_GRP0_0; in t7xx_pcie_mac_clear_set_int()
219 reg = IREG_BASE(t7xx_dev) + IMASK_HOST_MSIX_SET_GRP0_0; in t7xx_pcie_mac_clear_set_int()
244 void __iomem *reg = IREG_BASE(t7xx_dev) + MSIX_ISTAT_HST_GRP0_0; in t7xx_pcie_mac_clear_int_status()
261 iowrite32(val, IREG_BASE(t7xx_dev) + T7XX_PCIE_CFG_MSIX); in t7xx_pcie_set_mac_msix_cfg()
H A Dt7xx_pci.c64 void __iomem *ctrl_reg = IREG_BASE(t7xx_dev) + T7XX_PCIE_MISC_CTRL; in t7xx_dev_set_sleep_capability()
84 IREG_BASE(t7xx_dev) + T7XX_PCIE_RESOURCE_STATUS); in t7xx_wait_pm_config()
107 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in t7xx_pci_pm_init()
123 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in t7xx_pci_pm_init_late()
141 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in t7xx_pci_pm_reinit()
147 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in t7xx_pci_pm_exp_detected()
224 status = ioread32(IREG_BASE(t7xx_dev) + T7XX_PCIE_RESOURCE_STATUS); in t7xx_pci_disable_sleep()
287 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in __t7xx_pci_pm_suspend()
290 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in __t7xx_pci_pm_suspend()
328 iowrite32(T7XX_L1_BIT(0), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in __t7xx_pci_pm_suspend()
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H A Dt7xx_mhccif.c50 iowrite32(val, IREG_BASE(t7xx_dev) + DISABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
68 iowrite32(T7XX_L1_BIT(1), IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
73 iowrite32(val, IREG_BASE(t7xx_dev) + ENABLE_ASPM_LOWPWR); in t7xx_mhccif_isr_thread()
H A Dt7xx_pcie_mac.h21 #define IREG_BASE(t7xx_dev) ((t7xx_dev)->base_addr.pcie_mac_ireg_base) macro
H A Dt7xx_state_monitor.c344 false, IREG_BASE(md->t7xx_dev) + T7XX_PCIE_MISC_DEV_STATUS); in fsm_routine_start()
H A Dt7xx_modem_ops.c184 val = ioread32(IREG_BASE(t7xx_dev) + T7XX_PCIE_MISC_DEV_STATUS); in t7xx_reset_device_via_pmic()