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Searched refs:IP2APB_DDRPHY_IPS_BASE_ADDR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_utils.c19 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); in poll_pmu_message_ready()
27 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0); in ack_pmu_message_receive()
30 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004); in ack_pmu_message_receive()
33 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1); in ack_pmu_message_receive()
42 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); in get_mail()
55 reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032); in get_stream_message()
57 reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034); in get_stream_message()
H A Dddr4_init.c77 tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + in ddr_init()
H A Dhelper.c24 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h15 #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) macro
637 #define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
733 reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
735 reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))