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Searched refs:IOMMU_BASE (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/sparc64/
H A Dsun4u_iommu.c47 #define IOMMU_BASE 0x8 macro
101 baseaddr = is->regs[IOMMU_BASE >> 3]; in sun4u_translate_iommu()
212 case IOMMU_BASE: in iommu_mem_write()
214 is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; in iommu_mem_write()
215 is->regs[IOMMU_BASE >> 3] |= val << 32; in iommu_mem_write()
217 is->regs[IOMMU_BASE >> 3] = val; in iommu_mem_write()
220 case IOMMU_BASE + 0x4: in iommu_mem_write()
252 case IOMMU_BASE: in iommu_mem_read()
254 val = is->regs[IOMMU_BASE >> 3] >> 32; in iommu_mem_read()
256 val = is->regs[IOMMU_BASE >> 3]; in iommu_mem_read()
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/openbmc/qemu/hw/sparc/
H A Dsun4m_iommu.c58 #define IOMMU_BASE (0x0004 >> 2) macro
196 case IOMMU_BASE: in iommu_mem_write()
254 iopte = s->regs[IOMMU_BASE] << 4; in iommu_page_get_flags()