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Searched refs:INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11443 #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 macro
H A Ddce_10_0_sh_mask.h12505 #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 macro
H A Ddce_11_0_sh_mask.h12511 #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 macro
H A Ddce_11_2_sh_mask.h13127 #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_sh_mask.h106 #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK … macro