xref: /openbmc/linux/arch/x86/include/asm/intel-family.h (revision ed4543328f7108e1047b83b96ca7f7208747d930)
1  /* SPDX-License-Identifier: GPL-2.0 */
2  #ifndef _ASM_X86_INTEL_FAMILY_H
3  #define _ASM_X86_INTEL_FAMILY_H
4  
5  /*
6   * "Big Core" Processors (Branded as Core, Xeon, etc...)
7   *
8   * While adding a new CPUID for a new microarchitecture, add a new
9   * group to keep logically sorted out in chronological order. Within
10   * that group keep the CPUID for the variants sorted by model number.
11   *
12   * The defined symbol names have the following form:
13   *	INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
14   * where:
15   * OPTFAMILY	Describes the family of CPUs that this belongs to. Default
16   *		is assumed to be "_CORE" (and should be omitted). Other values
17   *		currently in use are _ATOM and _XEON_PHI
18   * MICROARCH	Is the code name for the micro-architecture for this core.
19   *		N.B. Not the platform name.
20   * OPTDIFF	If needed, a short string to differentiate by market segment.
21   *
22   *		Common OPTDIFFs:
23   *
24   *			- regular client parts
25   *		_L	- regular mobile parts
26   *		_G	- parts with extra graphics on
27   *		_X	- regular server parts
28   *		_D	- micro server parts
29   *		_N,_P	- other mobile parts
30   *		_H	- premium mobile parts
31   *		_S	- other client parts
32   *
33   *		Historical OPTDIFFs:
34   *
35   *		_EP	- 2 socket server parts
36   *		_EX	- 4+ socket server parts
37   *
38   * The #define line may optionally include a comment including platform or core
39   * names. An exception is made for skylake/kabylake where steppings seem to have gotten
40   * their own names :-(
41   */
42  
43  #define IFM(_fam, _model)	VFM_MAKE(X86_VENDOR_INTEL, _fam, _model)
44  
45  /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
46  #define INTEL_FAM6_ANY			X86_MODEL_ANY
47  /* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */
48  #define INTEL_ANY			IFM(X86_FAMILY_ANY, X86_MODEL_ANY)
49  
50  #define INTEL_FAM6_CORE_YONAH		0x0E
51  #define INTEL_CORE_YONAH		IFM(6, 0x0E)
52  
53  #define INTEL_FAM6_CORE2_MEROM		0x0F
54  #define INTEL_CORE2_MEROM		IFM(6, 0x0F)
55  #define INTEL_FAM6_CORE2_MEROM_L	0x16
56  #define INTEL_CORE2_MEROM_L		IFM(6, 0x16)
57  #define INTEL_FAM6_CORE2_PENRYN		0x17
58  #define INTEL_CORE2_PENRYN		IFM(6, 0x17)
59  #define INTEL_FAM6_CORE2_DUNNINGTON	0x1D
60  #define INTEL_CORE2_DUNNINGTON		IFM(6, 0x1D)
61  
62  #define INTEL_FAM6_NEHALEM		0x1E
63  #define INTEL_NEHALEM			IFM(6, 0x1E)
64  #define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
65  #define INTEL_NEHALEM_G			IFM(6, 0x1F) /* Auburndale / Havendale */
66  #define INTEL_FAM6_NEHALEM_EP		0x1A
67  #define INTEL_NEHALEM_EP		IFM(6, 0x1A)
68  #define INTEL_FAM6_NEHALEM_EX		0x2E
69  #define INTEL_NEHALEM_EX		IFM(6, 0x2E)
70  
71  #define INTEL_FAM6_WESTMERE		0x25
72  #define INTEL_WESTMERE			IFM(6, 0x25)
73  #define INTEL_FAM6_WESTMERE_EP		0x2C
74  #define INTEL_WESTMERE_EP		IFM(6, 0x2C)
75  #define INTEL_FAM6_WESTMERE_EX		0x2F
76  #define INTEL_WESTMERE_EX		IFM(6, 0x2F)
77  
78  #define INTEL_FAM6_SANDYBRIDGE		0x2A
79  #define INTEL_SANDYBRIDGE		IFM(6, 0x2A)
80  #define INTEL_FAM6_SANDYBRIDGE_X	0x2D
81  #define INTEL_SANDYBRIDGE_X		IFM(6, 0x2D)
82  #define INTEL_FAM6_IVYBRIDGE		0x3A
83  #define INTEL_IVYBRIDGE			IFM(6, 0x3A)
84  #define INTEL_FAM6_IVYBRIDGE_X		0x3E
85  #define INTEL_IVYBRIDGE_X		IFM(6, 0x3E)
86  
87  #define INTEL_FAM6_HASWELL		0x3C
88  #define INTEL_HASWELL			IFM(6, 0x3C)
89  #define INTEL_FAM6_HASWELL_X		0x3F
90  #define INTEL_HASWELL_X			IFM(6, 0x3F)
91  #define INTEL_FAM6_HASWELL_L		0x45
92  #define INTEL_HASWELL_L			IFM(6, 0x45)
93  #define INTEL_FAM6_HASWELL_G		0x46
94  #define INTEL_HASWELL_G			IFM(6, 0x46)
95  
96  #define INTEL_FAM6_BROADWELL		0x3D
97  #define INTEL_BROADWELL			IFM(6, 0x3D)
98  #define INTEL_FAM6_BROADWELL_G		0x47
99  #define INTEL_BROADWELL_G		IFM(6, 0x47)
100  #define INTEL_FAM6_BROADWELL_X		0x4F
101  #define INTEL_BROADWELL_X		IFM(6, 0x4F)
102  #define INTEL_FAM6_BROADWELL_D		0x56
103  #define INTEL_BROADWELL_D		IFM(6, 0x56)
104  
105  #define INTEL_FAM6_SKYLAKE_L		0x4E	/* Sky Lake             */
106  #define INTEL_SKYLAKE_L			IFM(6, 0x4E) /* Sky Lake */
107  #define INTEL_FAM6_SKYLAKE		0x5E	/* Sky Lake             */
108  #define INTEL_SKYLAKE			IFM(6, 0x5E) /* Sky Lake */
109  #define INTEL_FAM6_SKYLAKE_X		0x55	/* Sky Lake             */
110  #define INTEL_SKYLAKE_X			IFM(6, 0x55) /* Sky Lake */
111  /*                 CASCADELAKE_X	0x55	   Sky Lake -- s: 7     */
112  /*                 COOPERLAKE_X		0x55	   Sky Lake -- s: 11    */
113  
114  #define INTEL_FAM6_KABYLAKE_L		0x8E	/* Sky Lake             */
115  #define INTEL_KABYLAKE_L		IFM(6, 0x8E) /* Sky Lake */
116  /*                 AMBERLAKE_L		0x8E	   Sky Lake -- s: 9     */
117  /*                 COFFEELAKE_L		0x8E	   Sky Lake -- s: 10    */
118  /*                 WHISKEYLAKE_L	0x8E       Sky Lake -- s: 11,12 */
119  
120  #define INTEL_FAM6_KABYLAKE		0x9E	/* Sky Lake             */
121  #define INTEL_KABYLAKE			IFM(6, 0x9E) /* Sky Lake */
122  /*                 COFFEELAKE		0x9E	   Sky Lake -- s: 10-13 */
123  
124  #define INTEL_FAM6_COMETLAKE		0xA5	/* Sky Lake             */
125  #define INTEL_COMETLAKE			IFM(6, 0xA5) /* Sky Lake */
126  #define INTEL_FAM6_COMETLAKE_L		0xA6	/* Sky Lake             */
127  #define INTEL_COMETLAKE_L		IFM(6, 0xA6) /* Sky Lake */
128  
129  #define INTEL_FAM6_CANNONLAKE_L		0x66	/* Palm Cove */
130  #define INTEL_CANNONLAKE_L		IFM(6, 0x66) /* Palm Cove */
131  
132  #define INTEL_FAM6_ICELAKE_X		0x6A	/* Sunny Cove */
133  #define INTEL_ICELAKE_X			IFM(6, 0x6A) /* Sunny Cove */
134  #define INTEL_FAM6_ICELAKE_D		0x6C	/* Sunny Cove */
135  #define INTEL_ICELAKE_D			IFM(6, 0x6C) /* Sunny Cove */
136  #define INTEL_FAM6_ICELAKE		0x7D	/* Sunny Cove */
137  #define INTEL_ICELAKE			IFM(6, 0x7D) /* Sunny Cove */
138  #define INTEL_FAM6_ICELAKE_L		0x7E	/* Sunny Cove */
139  #define INTEL_ICELAKE_L			IFM(6, 0x7E) /* Sunny Cove */
140  #define INTEL_FAM6_ICELAKE_NNPI		0x9D	/* Sunny Cove */
141  #define INTEL_ICELAKE_NNPI		IFM(6, 0x9D) /* Sunny Cove */
142  
143  #define INTEL_FAM6_ROCKETLAKE		0xA7	/* Cypress Cove */
144  #define INTEL_ROCKETLAKE		IFM(6, 0xA7) /* Cypress Cove */
145  
146  #define INTEL_FAM6_TIGERLAKE_L		0x8C	/* Willow Cove */
147  #define INTEL_TIGERLAKE_L		IFM(6, 0x8C) /* Willow Cove */
148  #define INTEL_FAM6_TIGERLAKE		0x8D	/* Willow Cove */
149  #define INTEL_TIGERLAKE			IFM(6, 0x8D) /* Willow Cove */
150  
151  #define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */
152  #define INTEL_SAPPHIRERAPIDS_X		IFM(6, 0x8F) /* Golden Cove */
153  
154  #define INTEL_FAM6_EMERALDRAPIDS_X	0xCF
155  #define INTEL_EMERALDRAPIDS_X		IFM(6, 0xCF)
156  
157  #define INTEL_FAM6_GRANITERAPIDS_X	0xAD
158  #define INTEL_GRANITERAPIDS_X		IFM(6, 0xAD)
159  #define INTEL_FAM6_GRANITERAPIDS_D	0xAE
160  #define INTEL_GRANITERAPIDS_D		IFM(6, 0xAE)
161  
162  /* "Hybrid" Processors (P-Core/E-Core) */
163  
164  #define INTEL_FAM6_LAKEFIELD		0x8A	/* Sunny Cove / Tremont */
165  #define INTEL_LAKEFIELD			IFM(6, 0x8A) /* Sunny Cove / Tremont */
166  
167  #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
168  #define INTEL_ALDERLAKE			IFM(6, 0x97) /* Golden Cove / Gracemont */
169  #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */
170  #define INTEL_ALDERLAKE_L		IFM(6, 0x9A) /* Golden Cove / Gracemont */
171  
172  #define INTEL_FAM6_RAPTORLAKE		0xB7	/* Raptor Cove / Enhanced Gracemont */
173  #define INTEL_RAPTORLAKE		IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
174  #define INTEL_FAM6_RAPTORLAKE_P		0xBA
175  #define INTEL_RAPTORLAKE_P		IFM(6, 0xBA)
176  #define INTEL_FAM6_RAPTORLAKE_S		0xBF
177  #define INTEL_RAPTORLAKE_S		IFM(6, 0xBF)
178  
179  #define INTEL_FAM6_METEORLAKE		0xAC
180  #define INTEL_METEORLAKE		IFM(6, 0xAC)
181  #define INTEL_FAM6_METEORLAKE_L		0xAA
182  #define INTEL_METEORLAKE_L		IFM(6, 0xAA)
183  
184  #define INTEL_FAM6_ARROWLAKE_H		0xC5
185  #define INTEL_ARROWLAKE_H		IFM(6, 0xC5)
186  #define INTEL_FAM6_ARROWLAKE		0xC6
187  #define INTEL_ARROWLAKE			IFM(6, 0xC6)
188  #define INTEL_FAM6_ARROWLAKE_U		0xB5
189  #define INTEL_ARROWLAKE_U		IFM(6, 0xB5)
190  
191  #define INTEL_FAM6_LUNARLAKE_M		0xBD
192  #define INTEL_LUNARLAKE_M		IFM(6, 0xBD)
193  
194  /* "Small Core" Processors (Atom/E-Core) */
195  
196  #define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
197  #define INTEL_ATOM_BONNELL		IFM(6, 0x1C) /* Diamondville, Pineview */
198  #define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */
199  #define INTEL_ATOM_BONNELL_MID		IFM(6, 0x26) /* Silverthorne, Lincroft */
200  
201  #define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */
202  #define INTEL_ATOM_SALTWELL		IFM(6, 0x36) /* Cedarview */
203  #define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */
204  #define INTEL_ATOM_SALTWELL_MID		IFM(6, 0x27) /* Penwell */
205  #define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */
206  #define INTEL_ATOM_SALTWELL_TABLET	IFM(6, 0x35) /* Cloverview */
207  
208  #define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */
209  #define INTEL_ATOM_SILVERMONT		IFM(6, 0x37) /* Bay Trail, Valleyview */
210  #define INTEL_FAM6_ATOM_SILVERMONT_D	0x4D /* Avaton, Rangely */
211  #define INTEL_ATOM_SILVERMONT_D		IFM(6, 0x4D) /* Avaton, Rangely */
212  #define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */
213  #define INTEL_ATOM_SILVERMONT_MID	IFM(6, 0x4A) /* Merriefield */
214  
215  #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
216  #define INTEL_ATOM_AIRMONT		IFM(6, 0x4C) /* Cherry Trail, Braswell */
217  #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
218  #define INTEL_ATOM_AIRMONT_MID		IFM(6, 0x5A) /* Moorefield */
219  #define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
220  #define INTEL_ATOM_AIRMONT_NP		IFM(6, 0x75) /* Lightning Mountain */
221  
222  #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
223  #define INTEL_ATOM_GOLDMONT		IFM(6, 0x5C) /* Apollo Lake */
224  #define INTEL_FAM6_ATOM_GOLDMONT_D	0x5F /* Denverton */
225  #define INTEL_ATOM_GOLDMONT_D		IFM(6, 0x5F) /* Denverton */
226  
227  /* Note: the micro-architecture is "Goldmont Plus" */
228  #define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */
229  #define INTEL_ATOM_GOLDMONT_PLUS	IFM(6, 0x7A) /* Gemini Lake */
230  
231  #define INTEL_FAM6_ATOM_TREMONT_D	0x86 /* Jacobsville */
232  #define INTEL_ATOM_TREMONT_D		IFM(6, 0x86) /* Jacobsville */
233  #define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
234  #define INTEL_ATOM_TREMONT		IFM(6, 0x96) /* Elkhart Lake */
235  #define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */
236  #define INTEL_ATOM_TREMONT_L		IFM(6, 0x9C) /* Jasper Lake */
237  
238  #define INTEL_FAM6_ATOM_GRACEMONT	0xBE /* Alderlake N */
239  #define INTEL_ATOM_GRACEMONT		IFM(6, 0xBE) /* Alderlake N */
240  
241  #define INTEL_FAM6_ATOM_CRESTMONT_X	0xAF /* Sierra Forest */
242  #define INTEL_ATOM_CRESTMONT_X		IFM(6, 0xAF) /* Sierra Forest */
243  #define INTEL_FAM6_ATOM_CRESTMONT	0xB6 /* Grand Ridge */
244  #define INTEL_ATOM_CRESTMONT		IFM(6, 0xB6) /* Grand Ridge */
245  
246  #define INTEL_FAM6_ATOM_DARKMONT_X	0xDD /* Clearwater Forest */
247  #define INTEL_ATOM_DARKMONT_X		IFM(6, 0xDD) /* Clearwater Forest */
248  
249  /* Xeon Phi */
250  
251  #define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
252  #define INTEL_XEON_PHI_KNL		IFM(6, 0x57) /* Knights Landing */
253  #define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */
254  #define INTEL_XEON_PHI_KNM		IFM(6, 0x85) /* Knights Mill */
255  
256  /* Family 5 */
257  #define INTEL_FAM5_QUARK_X1000		0x09 /* Quark X1000 SoC */
258  #define INTEL_QUARK_X1000		IFM(5, 0x09) /* Quark X1000 SoC */
259  
260  #endif /* _ASM_X86_INTEL_FAMILY_H */
261