| /openbmc/qemu/target/avr/ |
| H A D | disas.c | 103 #define INSN(opcode, format, ...) \ macro
140 INSN(ADD, "r%d, r%d", a->rd, a->rr)
141 INSN(ADC, "r%d, r%d", a->rd, a->rr)
142 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
143 INSN(SUB, "r%d, r%d", a->rd, a->rr)
144 INSN(SUBI, "r%d, %d", a->rd, a->imm)
145 INSN(SBC, "r%d, r%d", a->rd, a->rr)
146 INSN(SBCI, "r%d, %d", a->rd, a->imm)
147 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
148 INSN(AND, "r%d, r%d", a->rd, a->rr)
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| /openbmc/qemu/target/openrisc/ |
| H A D | disas.c | 53 #define INSN(opcode, format, ...) \ macro
60 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
61 INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
62 INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
63 INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
64 INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
65 INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
66 INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
67 INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b)
68 INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b)
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| /openbmc/qemu/target/loongarch/ |
| H A D | disas.c | 123 #define output(C, INSN, FMT, ...) \ argument
127 (C)->insn, INSN, ##__VA_ARGS__); \
130 INSN, ##__VA_ARGS__); \
349 #define INSN(insn, type) \ macro
356 INSN(clo_w, rr) in INSN() function
357 INSN(clz_w, rr) in INSN()
358 INSN(cto_w, rr) in INSN()
359 INSN(ctz_w, rr) in INSN()
360 INSN(clo_d, rr) in INSN()
361 INSN(clz_d, rr) in INSN()
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | usr.c | 51 #define FUNC_x_OP_x(RESTYPE, SRCTYPE, NAME, INSN) \ argument
57 INSN "\n\t" \
66 #define FUNC_R_OP_R(NAME, INSN) \ argument
67 FUNC_x_OP_x(uint32_t, uint32_t, NAME, INSN)
69 #define FUNC_R_OP_P(NAME, INSN) \ argument
70 FUNC_x_OP_x(uint32_t, uint64_t, NAME, INSN)
72 #define FUNC_P_OP_P(NAME, INSN) \ argument
73 FUNC_x_OP_x(uint64_t, uint64_t, NAME, INSN)
75 #define FUNC_P_OP_R(NAME, INSN) \ argument
76 FUNC_x_OP_x(uint64_t, uint32_t, NAME, INSN)
[all …]
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| /openbmc/qemu/tests/tcg/ppc64/ |
| H A D | non_signalling_xscv.c | 6 #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ argument
12 INSN " 32, 32\n\t" \
19 printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
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| H A D | vsx_f2i_nan.c | 11 #define DEFINE_VSX_F2I_FUNC(SRC_T, DEST_T, INSN) \ argument
16 asm(#INSN " %x0, %x1" : "=wa" (result) : "wa" (v)); \
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | translate-mve.c | 531 #define DO_1OP_VEC(INSN, FN, VECFN) \ argument
532 static bool trans_##INSN(DisasContext *s, arg_1op *a) \
543 #define DO_1OP(INSN, FN) DO_1OP_VEC(INSN, FN, NULL) argument
558 #define DO_VCVT(INSN, HFN, SFN) \ in DO_1OP() argument
559 static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ in DO_1OP()
563 static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
567 static bool trans_##INSN(DisasContext *s, arg_1op *a) \
571 gen_##INSN##h, \
572 gen_##INSN##s, \
620 #define DO_VCVT_RMODE(INSN, RMODE, U) \ argument
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| H A D | translate-vfp.c | 2255 #define MAKE_ONE_VFM_TRANS_FN(INSN, PREC, NEGN, NEGD) \ argument
2256 static bool trans_##INSN##_##PREC(DisasContext *s, \
2257 arg_##INSN##_##PREC *a) \
2393 #define DO_VFP_2OP(INSN, PREC, FN, CHECK) \ argument
2394 static bool trans_##INSN##_##PREC(DisasContext *s, \
2395 arg_##INSN##_##PREC *a) \
2403 #define DO_VFP_VMOV(INSN, PREC, FN) \ argument
2404 static bool trans_##INSN##_##PREC(DisasContext *s, \
2405 arg_##INSN##_##PREC *a) \
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| H A D | mve_helper.c | 1849 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \ argument
1850 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \
1851 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \
1852 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC)
1854 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \ argument
1855 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \
1856 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \
1857 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC)
1952 #define DO_VMAXMINV_U(INSN, FN) \ argument
1953 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \
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| /openbmc/qemu/tests/tcg/hppa/ |
| H A D | stby.c | 41 #define TEST(INSN, OFS, E) \ argument
44 asm volatile(INSN " %1, " #OFS "(%0)" \
46 check(&s, E, which, INSN, OFS); \
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| /openbmc/qemu/disas/ |
| H A D | sparc.c | 2265 #define HASH_INSN(INSN) \ argument
2266 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
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